This application relates to analysis of integrated circuits.
Circuits may be viewed as networks of nodes and circuit components connected between nodes. As such, circuits may be analyzed based on a nodal analysis where a nodal equation may be written for each node based on the conservation of charge at the node, i.e., the total current entering the node is equal to the total current leaving the node (the Kirchoff's second rule). For a circuit with N nodes, N equations for the N nodes can be expressed in terms of the properties of circuit components such as resistance, capacitance, and inductance, and in terms of the node voltages and currents. These N equations can be written into a matrix equation and are solved using various matrix approaches such as LU decompositions of matrices. For circuits with certain control sources, inductance and current control sources, additional equations for different current branches may be added to fully describe the circuits.
Power network analysis may be performed based on the circuit matrix equations to investigate behaviors of circuit networks such as voltage drop, voltage oscillation, and electromigration. Excessive voltage drops may reduce the switching speed as well as the noise margins of circuits and may even cause logic failures under some circumstances. Electromigration may decrease the chip lifetime. Moreover voltage oscillation may occur when power network resonance frequency drops to the range of the signal frequency.
One bottleneck of the power network analysis based on the above nodal analysis is the tremendous amount of variables in large power networks such as integrated circuits. One well-known circuit analysis software program for solving such circuit equations is the SPICE circuit simulator originally developed by the University of California at Berkeley. The SPICE uses the LU decomposition of a matrix to solve the circuit equations. As the number of the circuit elements and nodes increases, the super linear complexity of the LU deposition method and other direct methods make them prohibitive for large-scale circuits.
The power networks are mostly linear circuit networks. There are other more complex circuits such as circuits with transistors which exhibit nonlinear circuit properties. Matrices for circuits with transistors may be solved by, e.g., direct simulation methods like LU decomposition used in the Berkeley SPICE2 simulator and its variations. See, Nagal, “Spice2: A computer program to simulate semiconductor circuits,” Tech. Rep. ERL M520, Electronics Research Laboratory Report, UC Berkeley (1975). The direct simulation methods may become less effective and can reach their computational limits when the number of transistors in circuit networks increases and the circuit configurations become complex. This is in part because the super linear complexity O(n1.5) increases with the number of circuit nodes, n, and the amount of the extracted interconnect data for a large n can exceed the capacity of the software based on a direct simulation method.
Various other transistor-level simulation methods have been developed to address the limitations of the direct simulation methods, some of which, however, have trade-offs in certain aspects such as the simulation accuracy in comparison with the direct simulation methods. Examples of other transistor-level simulation methods include application of different integration methods (explicit or implicit) on subcircuits according to their activities by Sakallah and Director in “SAMSON2: An event driven VLSI circuit simulator,” IEEE Trans. On Computer-Aided Design ICs and Systems, Vol. 4(4), pp. 668-684 (1985), and reduction of the number and cost of LU decompositions by using low cost integration approximation and simpler linearization via successive C=chord method) by Li and Shi in “SILCA: Fast-yet-accurate time-domain simulation of VLSI circuits with strong parasitic coupling effects,” ICCAD, pp. 793-799 (2003). Various fast simulation tools for transistor-level simulation are also commercially available from companies such as Nassda Corporation (www.nassda.com), Synopsys, Inc.(www.synopsys.com), Apache Design Solutions, Inc. (www.apachedesignsolutions.com) and Cadence Design Systems (www.cadence.com). These commercial simulation software tools usually partition a circuit into subcircuits which can be simulated with different time steps to explore latency but can have potential convergence problems due to the coupling effects or strong feedback in the circuits. The convergence rate may also be sensitive to the partition algorithm and propagation order.